This invention relates to a semiconductive memory device, and more particularly, to a semiconductive memory device capable of carrying out a read-out operation at a high speed.
In general, a multivalued semiconductive memory device is known which memorizes digital data having at least two bits in a memory transistor. In a conventional multivalued semiconductive memory device, the digital data are defined in correspondence to threshold levels of the memory transistor. It will be assumed that the digital data has a lower datum and an upper datum. On carrying out a read-out operation, a read-out voltage is applied to the memory transistor in an ascending order from a lower voltage to a higher voltage in order to determine the digital data. The lower datum is determined at first and the upper datum is secondly determined when the read-out voltage is applied to the memory transistor in the ascending order from the lower voltage to the higher voltage.
However, it is difficult to carry out the read-out operation in the conventional multivalued semiconductive memory device at a high speed when the read-out voltage is applied to the memory transistor in the ascending order from the lower voltage to the higher voltage.
In order to carry out the read-out operation at the high speed, it is known that an improved multivalued semiconductive memory device comprises first and second reading sections which carry out a data reading operation and a data output operation by turns. In other words, the first reading section carries out the data reading operation when the second reading section carries out the data output operation. When the second reading section carries out the data reading operation, the first reading section carries out the data output operation.
However, the improved multivalued semiconductive memory device has a large size and increases a consumption of electric power inasmuch as the improved multivalued semiconductive memory device comprises first and second reading sections.
In addition, another multivalued semiconductive memory device is disclosed in Japanese Patent Publication Tokkai Hei 10-11979 (11979/1998). In the multivalued semiconductive memory device, first through third word line voltages are selectively supplied to a line in order to judge digital data memorized in the memory transistor. More particularly, the second word line voltage is firstly supplied to the word line. In accordance with a read-out result based on the second word line voltage, a selected one of the first and the third word line voltage is secondly supplied to the word line.
Inasmuch as the second word line voltage is firstly supplied to the word line and the selected one of the first and the third word line voltage is secondly supplied to the word lines in accordance with the read-out result based on the second word line voltage, it is difficult to carry out the read-out operation at the high speed.